On Wed, 20 Jun 2012, Lluís Batlle i Rossell wrote: > > > Well, I think I take my words back. Handling the ldc1/sdc1 cases in MIPS32 is > > > tricker than I thought first, because I can't use ldl/ldr or sdl/sdr there. > > > Given my ability with mips assembly, I leave the patch as is. I suggest that for 32-bit kernels you simply reuse the existing snippets from that function and handle ldc1/sdc1 with a pair of lwl/ldr or swl/swr pairs ordered as appropriate for the endianness selected -- that should be fairly easy. Also regardless of that, please make sure that your code handles the two possible settings of CP0 Status register's bit FR correctly, as the 32-bit halves of floating-point data are distributed differently across floating-point registers based on this bit's setting (check if an o32 and an n64 or n32 program gets these values right). > > why is there a reason for this ? Unaligned FPU access shouts to me simply > > broken code, go fix that. But maybe I'm wrong ? Since we're emulating these accesses at all I concur Lluís we should stay consistent across the whole instruction set. > Right, the patch allows broken code to run further, instead of fail straight. > The crash can be still achieved disabling the emulation of unaligned accesses > completely, through debugfs, for example. sysmips(MIPS_FIXADE, 0) is another way. > As Jonas reported, I think that maybe I should rework the patch for it to emit > sigbus instead of sigill on ldc1,ldc1 for mips32. Do I understand it right? Have you checked your code against a non-FPU processor (or with the "nofpu" kernel option) too? Maciej
