Hello, On Sat, Jun 16, 2012 at 02:15:13PM +0200, Lluís Batlle i Rossell wrote: > On Sat, Jun 16, 2012 at 01:21:27PM +0200, Jonas Gorski wrote: > > On 16 June 2012 00:22, Lluis Batlle i Rossell <viric@xxxxxxxxxx> wrote: > > > Reusing most of the code from lw,ld,sw,sd emulation, > > > I add the emulation for lwc1,ldc1,swc1,sdc1. > > > > What about lwxc1, ldxc1, swxc1 and sdxc1? These also require alignment. > > Looking at gcc code, I could not find those instructions emmitted. I could write > some assembly tests cases though. I just undesrtood the Loongson2f only does MIPS III, and the *xc1 instructions are for MIPS IV, which I don't have, so I can't test. I started to write the handling of cop1x_op, then a switch() of the coprocessor operation, then I had to introduce a new instruction format not available in inst.h, ... too much new lines I won't be able to test. I'll repost only with the attention on MIPS II ldc1/sdc1. Btw, mips-iv.pdf says in the LDC1 page that it's MIPS II, but Table B-5 mentions it as MIPS III. I imagine the table is wrong, because it appears in Table B-25 too. Regards, Lluís.
