On Sun, Oct 2, 2011 at 4:30 PM, Jayachandran C.
<jayachandranc@xxxxxxxxxxxxxxxxx> wrote:
> On Sun, Oct 02, 2011 at 03:26:14PM +0800, Hillf Danton wrote:
>> Netlogic XLR chip has multiple cores. Each core includes four integrated
>> hardware threads, and they share L1 data and instruction caches.
>>
>> If XLR chip is marked to be SMT capable, linux scheduler then could do more,
>> say idle load balancing.
>>
>> Any comment is welcom, thanks.
>
> I may be missing something here, but how about just setting cpu_data[].core in
> the init_secondary method? That would avoid the change to kernel/smp.c.
>
Got and thanks. It is re-prepared as the following:)
Hillf
----------------------------------------------------------------------------
Subject: [RFC] Mark Netlogic XLR chip to be SMT capable
Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.
If XLR chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.
According to JC's comment changes are now confined only to the code of XLR.
Signed-off-by: Hillf Danton <dhillf@xxxxxxxxx>
---
--- a/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:28 2011
+++ b/arch/mips/netlogic/xlr/smp.c Mon Oct 3 13:33:02 2011
@@ -104,6 +104,12 @@ void nlm_early_init_secondary(void)
*/
static void __cpuinit nlm_init_secondary(void)
{
+ unsigned int cpu, core_id;
+
+ cpu = smp_processor_id();
+ core_id = (cpu >> 2) & 0x7;
+ cpu_data[cpu].core = core_id;
+
nlm_smp_irq_init();
}
@@ -176,6 +182,8 @@ void __init nlm_smp_setup(void)
void nlm_prepare_cpus(unsigned int max_cpus)
{
+ /* declare we are SMT capable */
+ smp_num_siblings = 4;
}
struct plat_smp_ops nlm_smp_ops = {
