On Sun, Oct 02, 2011 at 03:26:14PM +0800, Hillf Danton wrote:
> Netlogic XLR chip has multiple cores. Each core includes four integrated
> hardware threads, and they share L1 data and instruction caches.
>
> If XLR chip is marked to be SMT capable, linux scheduler then could do more,
> say idle load balancing.
>
> Any comment is welcom, thanks.
I may be missing something here, but how about just setting cpu_data[].core in
the init_secondary method? That would avoid the change to kernel/smp.c.
>
> Signed-off-by: Hillf Danton <dhillf@xxxxxxxxx>
> ---
>
> --- a/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:28 2011
> +++ b/arch/mips/netlogic/xlr/smp.c Sun Oct 2 14:15:58 2011
> @@ -176,6 +176,7 @@ void __init nlm_smp_setup(void)
>
> void nlm_prepare_cpus(unsigned int max_cpus)
> {
> + smp_num_siblings = 4;
> }
>
> struct plat_smp_ops nlm_smp_ops = {
> --- a/arch/mips/kernel/smp.c Sun Oct 2 14:12:09 2011
> +++ b/arch/mips/kernel/smp.c Sun Oct 2 14:14:58 2011
> @@ -73,7 +73,12 @@ static inline void set_cpu_sibling_map(i
>
> if (smp_num_siblings > 1) {
> for_each_cpu_mask(i, cpu_sibling_setup_map) {
> - if (cpu_data[cpu].core == cpu_data[i].core) {
> + if (current_cpu_type() == CPU_XLR) {
> + if (((i>>2) & 0x7) == ((cpu>>2) & 0x7))
> + goto set;
> + }
> + else if (cpu_data[cpu].core == cpu_data[i].core) {
> +set:
> cpu_set(i, cpu_sibling_map[cpu]);
> cpu_set(cpu, cpu_sibling_map[i]);
> }
JC.
