Hi,
On 10 June 2011 23:47, Maxime Bizon <mbizon@xxxxxxxxxx> wrote:
> Needed for upcoming 6368 CPU support.
>
> Signed-off-by: Maxime Bizon <mbizon@xxxxxxxxxx>
> ---
> Âarch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h Â| Â183 +++++++++++++++++++++
> Âarch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | Â 78 +++++++++
> Â2 files changed, 261 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> index 464f948..ce6b3ca 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> @@ -88,6 +88,7 @@ enum bcm63xx_regs_set {
> Â Â Â ÂRSET_UART1,
> Â Â Â ÂRSET_GPIO,
> Â Â Â ÂRSET_SPI,
> + Â Â Â RSET_SPI2,
What's the difference between SPI and SPI2?
As far as I can tell the biggest difference between the bcm6338/48 SPI
controller and the bcm6358/68 one is the order of the registers (and
some bit positions), but the general way it works is the same. Unless
you have two drivers (which will then probably have a lot of common
code), you'll need to check the chipid anyway to know which RSET to
use, so you could also just direcly use this to use the correct
register offsets.
The High-Speed SPI controller on the bcm6328, bcm63268 and bcm6362 is
a totally different beast though, that one should get it's own
register set (but that's in the future ;-).
> Â Â Â ÂRSET_UDC0,
> Â Â Â ÂRSET_OHCI0,
> Â Â Â ÂRSET_OHCI_PRIV,
> @@ -98,10 +99,23 @@ enum bcm63xx_regs_set {
> Â Â Â ÂRSET_ENET0,
> Â Â Â ÂRSET_ENET1,
> Â Â Â ÂRSET_ENETDMA,
> + Â Â Â RSET_ENETDMAC,
> + Â Â Â RSET_ENETDMAS,
> + Â Â Â RSET_ENETSW,
> Â Â Â ÂRSET_EHCI0,
> Â Â Â ÂRSET_SDRAM,
> Â Â Â ÂRSET_MEMC,
> Â Â Â ÂRSET_DDR,
> + Â Â Â RSET_M2M,
> + Â Â Â RSET_ATM,
> + Â Â Â RSET_XTM,
> + Â Â Â RSET_XTMDMA,
> + Â Â Â RSET_XTMDMAC,
> + Â Â Â RSET_XTMDMAS,
> + Â Â Â RSET_PCM,
> + Â Â Â RSET_PCMDMA,
> + Â Â Â RSET_PCMDMAC,
> + Â Â Â RSET_PCMDMAS,
> Â};
>
> Â#define RSET_DSL_LMEM_SIZE Â Â Â Â Â Â (64 * 1024 * 4)
> @@ -109,11 +123,18 @@ enum bcm63xx_regs_set {
> Â#define RSET_WDT_SIZE Â Â Â Â Â Â Â Â Â12
> Â#define RSET_ENET_SIZE Â Â Â Â Â Â Â Â 2048
> Â#define RSET_ENETDMA_SIZE Â Â Â Â Â Â Â2048
> +#define RSET_ENETSW_SIZE Â Â Â Â Â Â Â 65536
> Â#define RSET_UART_SIZE Â Â Â Â Â Â Â Â 24
> Â#define RSET_UDC_SIZE Â Â Â Â Â Â Â Â Â256
> Â#define RSET_OHCI_SIZE Â Â Â Â Â Â Â Â 256
> Â#define RSET_EHCI_SIZE Â Â Â Â Â Â Â Â 256
> Â#define RSET_PCMCIA_SIZE Â Â Â Â Â Â Â 12
> +#define RSET_M2M_SIZE Â Â Â Â Â Â Â Â Â256
> +#define RSET_ATM_SIZE Â Â Â Â Â Â Â Â Â4096
> +#define RSET_XTM_SIZE Â Â Â Â Â Â Â Â Â10240
> +#define RSET_XTMDMA_SIZE Â Â Â Â Â Â Â 256
> +#define RSET_XTMDMAC_SIZE(chans) Â Â Â (16 * (chans))
> +#define RSET_XTMDMAS_SIZE(chans) Â Â Â (16 * (chans))
>
> Â/*
> Â* 6338 register sets base address
> @@ -127,6 +148,7 @@ enum bcm63xx_regs_set {
> Â#define BCM_6338_UART1_BASE Â Â Â Â Â Â(0xdeadbeef)
> Â#define BCM_6338_GPIO_BASE Â Â Â Â Â Â (0xfffe0400)
> Â#define BCM_6338_SPI_BASE Â Â Â Â Â Â Â(0xfffe0c00)
> +#define BCM_6338_SPI2_BASE Â Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6338_UDC0_BASE Â Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6338_USBDMA_BASE Â Â Â Â Â (0xfffe2400)
> Â#define BCM_6338_OHCI0_BASE Â Â Â Â Â Â(0xdeadbeef)
> @@ -141,10 +163,23 @@ enum bcm63xx_regs_set {
> Â#define BCM_6338_ENET0_BASE Â Â Â Â Â Â(0xfffe2800)
> Â#define BCM_6338_ENET1_BASE Â Â Â Â Â Â(0xdeadbeef)
> Â#define BCM_6338_ENETDMA_BASE Â Â Â Â Â(0xfffe2400)
> +#define BCM_6338_ENETDMAC_BASE Â Â Â Â (0xfffe2500)
> +#define BCM_6338_ENETDMAS_BASE Â Â Â Â (0xfffe2600)
> +#define BCM_6338_ENETSW_BASE Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6338_EHCI0_BASE Â Â Â Â Â Â(0xdeadbeef)
> Â#define BCM_6338_SDRAM_BASE Â Â Â Â Â Â(0xfffe3100)
> Â#define BCM_6338_MEMC_BASE Â Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6338_DDR_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6338_M2M_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6338_ATM_BASE Â Â Â Â Â Â Â(0xdeadbeef)
That one is already there, it's called BCM_6338_SAR_BASE. You should
just rename that one.
> +#define BCM_6338_XTM_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6338_XTMDMA_BASE Â Â Â Â Â (0xdeadbeef)
> +#define BCM_6338_XTMDMAC_BASE Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6338_XTMDMAS_BASE Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6338_PCM_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6338_PCMDMA_BASE Â Â Â Â Â (0xdeadbeef)
> +#define BCM_6338_PCMDMAC_BASE Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6338_PCMDMAS_BASE Â Â Â Â Â(0xdeadbeef)
>
> Â/*
> Â* 6345 register sets base address
> @@ -158,10 +193,14 @@ enum bcm63xx_regs_set {
> Â#define BCM_6345_UART1_BASE Â Â Â Â Â Â(0xdeadbeef)
> Â#define BCM_6345_GPIO_BASE Â Â Â Â Â Â (0xfffe0400)
> Â#define BCM_6345_SPI_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6345_SPI2_BASE Â Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6345_UDC0_BASE Â Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6345_USBDMA_BASE Â Â Â Â Â (0xfffe2800)
> Â#define BCM_6345_ENET0_BASE Â Â Â Â Â Â(0xfffe1800)
> Â#define BCM_6345_ENETDMA_BASE Â Â Â Â Â(0xfffe2800)
> +#define BCM_6345_ENETDMAC_BASE Â Â Â Â (0xfffe2900)
> +#define BCM_6345_ENETDMAS_BASE Â Â Â Â (0xfffe2a00)
> +#define BCM_6345_ENETSW_BASE Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6345_PCMCIA_BASE Â Â Â Â Â (0xfffe2028)
> Â#define BCM_6345_MPI_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> Â#define BCM_6345_OHCI0_BASE Â Â Â Â Â Â(0xfffe2100)
> @@ -176,6 +215,16 @@ enum bcm63xx_regs_set {
> Â#define BCM_6345_SDRAM_BASE Â Â Â Â Â Â(0xfffe2300)
> Â#define BCM_6345_MEMC_BASE Â Â Â Â Â Â (0xdeadbeef)
> Â#define BCM_6345_DDR_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6345_M2M_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6345_ATM_BASE Â Â Â Â Â Â Â(0xdeadbeef)
Actually that would be 0xfffe4000 (same as the bcm6348). There's also
a SAR_BASE which should be removed.
Jonas
