Hi Maxime,
On 10 June 2011 23:47, Maxime Bizon <mbizon@xxxxxxxxxx> wrote:
> Use preprocessor when possible to avoid duplicated and error-prone
> code.
>
> Signed-off-by: Maxime Bizon <mbizon@xxxxxxxxxx>
> ---
> Âarch/mips/bcm63xx/cpu.c             Â| Â145 +----------
> Âarch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | Â311 +++++++---------------
> Â2 files changed, 109 insertions(+), 347 deletions(-)
>
> diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
> index 7c7e4d4..027ac30 100644
> --- a/arch/mips/bcm63xx/cpu.c
> +++ b/arch/mips/bcm63xx/cpu.c
> @@ -33,162 +33,37 @@ static unsigned int bcm63xx_memory_size;
> Â* 6338 register sets and irqs
> Â*/
> Âstatic const unsigned long bcm96338_regs_base[] = {
I would propose naming these bcm63??_regs_base; it would be more in
line with the rest of the code.
> - Â Â Â [RSET_DSL_LMEM] Â Â Â Â = BCM_6338_DSL_LMEM_BASE,
> - Â Â Â [RSET_PERF] Â Â Â Â Â Â = BCM_6338_PERF_BASE,
> - Â Â Â [RSET_TIMER] Â Â Â Â Â Â= BCM_6338_TIMER_BASE,
> - Â Â Â [RSET_WDT] Â Â Â Â Â Â Â= BCM_6338_WDT_BASE,
> - Â Â Â [RSET_UART0] Â Â Â Â Â Â= BCM_6338_UART0_BASE,
> - Â Â Â [RSET_UART1] Â Â Â Â Â Â= BCM_6338_UART1_BASE,
> - Â Â Â [RSET_GPIO] Â Â Â Â Â Â = BCM_6338_GPIO_BASE,
> - Â Â Â [RSET_SPI] Â Â Â Â Â Â Â= BCM_6338_SPI_BASE,
> - Â Â Â [RSET_OHCI0] Â Â Â Â Â Â= BCM_6338_OHCI0_BASE,
> - Â Â Â [RSET_OHCI_PRIV] Â Â Â Â= BCM_6338_OHCI_PRIV_BASE,
> - Â Â Â [RSET_USBH_PRIV] Â Â Â Â= BCM_6338_USBH_PRIV_BASE,
> - Â Â Â [RSET_UDC0] Â Â Â Â Â Â = BCM_6338_UDC0_BASE,
> - Â Â Â [RSET_MPI] Â Â Â Â Â Â Â= BCM_6338_MPI_BASE,
> - Â Â Â [RSET_PCMCIA] Â Â Â Â Â = BCM_6338_PCMCIA_BASE,
> - Â Â Â [RSET_SDRAM] Â Â Â Â Â Â= BCM_6338_SDRAM_BASE,
> - Â Â Â [RSET_DSL] Â Â Â Â Â Â Â= BCM_6338_DSL_BASE,
> - Â Â Â [RSET_ENET0] Â Â Â Â Â Â= BCM_6338_ENET0_BASE,
> - Â Â Â [RSET_ENET1] Â Â Â Â Â Â= BCM_6338_ENET1_BASE,
> - Â Â Â [RSET_ENETDMA] Â Â Â Â Â= BCM_6338_ENETDMA_BASE,
> - Â Â Â [RSET_MEMC] Â Â Â Â Â Â = BCM_6338_MEMC_BASE,
> - Â Â Â [RSET_DDR] Â Â Â Â Â Â Â= BCM_6338_DDR_BASE,
> + Â Â Â __GEN_CPU_REGS_TABLE(6338)
> Â};
>
> Âstatic const int bcm96338_irqs[] = {
> - Â Â Â [IRQ_TIMER] Â Â Â Â Â Â = BCM_6338_TIMER_IRQ,
> - Â Â Â [IRQ_UART0] Â Â Â Â Â Â = BCM_6338_UART0_IRQ,
> - Â Â Â [IRQ_DSL] Â Â Â Â Â Â Â = BCM_6338_DSL_IRQ,
> - Â Â Â [IRQ_ENET0] Â Â Â Â Â Â = BCM_6338_ENET0_IRQ,
> - Â Â Â [IRQ_ENET_PHY] Â Â Â Â Â= BCM_6338_ENET_PHY_IRQ,
> - Â Â Â [IRQ_ENET0_RXDMA] Â Â Â = BCM_6338_ENET0_RXDMA_IRQ,
> - Â Â Â [IRQ_ENET0_TXDMA] Â Â Â = BCM_6338_ENET0_TXDMA_IRQ,
> + Â Â Â __GEN_CPU_IRQ_TABLE(6338)
> Â};
>
> -/*
> - * 6345 register sets and irqs
> - */
You should leave the comment here (or also delete the 6338 one on top).
> Âstatic const unsigned long bcm96345_regs_base[] = {
> - Â Â Â [RSET_DSL_LMEM] Â Â Â Â = BCM_6345_DSL_LMEM_BASE,
> - Â Â Â [RSET_PERF] Â Â Â Â Â Â = BCM_6345_PERF_BASE,
> - Â Â Â [RSET_TIMER] Â Â Â Â Â Â= BCM_6345_TIMER_BASE,
> - Â Â Â [RSET_WDT] Â Â Â Â Â Â Â= BCM_6345_WDT_BASE,
> - Â Â Â [RSET_UART0] Â Â Â Â Â Â= BCM_6345_UART0_BASE,
> - Â Â Â [RSET_UART1] Â Â Â Â Â Â= BCM_6345_UART1_BASE,
> - Â Â Â [RSET_GPIO] Â Â Â Â Â Â = BCM_6345_GPIO_BASE,
> - Â Â Â [RSET_SPI] Â Â Â Â Â Â Â= BCM_6345_SPI_BASE,
> - Â Â Â [RSET_UDC0] Â Â Â Â Â Â = BCM_6345_UDC0_BASE,
> - Â Â Â [RSET_OHCI0] Â Â Â Â Â Â= BCM_6345_OHCI0_BASE,
> - Â Â Â [RSET_OHCI_PRIV] Â Â Â Â= BCM_6345_OHCI_PRIV_BASE,
> - Â Â Â [RSET_USBH_PRIV] Â Â Â Â= BCM_6345_USBH_PRIV_BASE,
> - Â Â Â [RSET_MPI] Â Â Â Â Â Â Â= BCM_6345_MPI_BASE,
> - Â Â Â [RSET_PCMCIA] Â Â Â Â Â = BCM_6345_PCMCIA_BASE,
> - Â Â Â [RSET_DSL] Â Â Â Â Â Â Â= BCM_6345_DSL_BASE,
> - Â Â Â [RSET_ENET0] Â Â Â Â Â Â= BCM_6345_ENET0_BASE,
> - Â Â Â [RSET_ENET1] Â Â Â Â Â Â= BCM_6345_ENET1_BASE,
> - Â Â Â [RSET_ENETDMA] Â Â Â Â Â= BCM_6345_ENETDMA_BASE,
> - Â Â Â [RSET_EHCI0] Â Â Â Â Â Â= BCM_6345_EHCI0_BASE,
> - Â Â Â [RSET_SDRAM] Â Â Â Â Â Â= BCM_6345_SDRAM_BASE,
> - Â Â Â [RSET_MEMC] Â Â Â Â Â Â = BCM_6345_MEMC_BASE,
> - Â Â Â [RSET_DDR] Â Â Â Â Â Â Â= BCM_6345_DDR_BASE,
> + Â Â Â __GEN_CPU_REGS_TABLE(6345)
> Â};
>
> Âstatic const int bcm96345_irqs[] = {
> - Â Â Â [IRQ_TIMER] Â Â Â Â Â Â = BCM_6345_TIMER_IRQ,
> - Â Â Â [IRQ_UART0] Â Â Â Â Â Â = BCM_6345_UART0_IRQ,
> - Â Â Â [IRQ_DSL] Â Â Â Â Â Â Â = BCM_6345_DSL_IRQ,
> - Â Â Â [IRQ_ENET0] Â Â Â Â Â Â = BCM_6345_ENET0_IRQ,
> - Â Â Â [IRQ_ENET_PHY] Â Â Â Â Â= BCM_6345_ENET_PHY_IRQ,
> - Â Â Â [IRQ_ENET0_RXDMA] Â Â Â = BCM_6345_ENET0_RXDMA_IRQ,
> - Â Â Â [IRQ_ENET0_TXDMA] Â Â Â = BCM_6345_ENET0_TXDMA_IRQ,
> + Â Â Â __GEN_CPU_IRQ_TABLE(6345)
> Â};
>
> -/*
> - * 6348 register sets and irqs
> - */
Same comment comment.
> Âstatic const unsigned long bcm96348_regs_base[] = {
> - Â Â Â [RSET_DSL_LMEM] Â Â Â Â = BCM_6348_DSL_LMEM_BASE,
> - Â Â Â [RSET_PERF] Â Â Â Â Â Â = BCM_6348_PERF_BASE,
> - Â Â Â [RSET_TIMER] Â Â Â Â Â Â= BCM_6348_TIMER_BASE,
> - Â Â Â [RSET_WDT] Â Â Â Â Â Â Â= BCM_6348_WDT_BASE,
> - Â Â Â [RSET_UART0] Â Â Â Â Â Â= BCM_6348_UART0_BASE,
> - Â Â Â [RSET_UART1] Â Â Â Â Â Â= BCM_6348_UART1_BASE,
> - Â Â Â [RSET_GPIO] Â Â Â Â Â Â = BCM_6348_GPIO_BASE,
> - Â Â Â [RSET_SPI] Â Â Â Â Â Â Â= BCM_6348_SPI_BASE,
> - Â Â Â [RSET_OHCI0] Â Â Â Â Â Â= BCM_6348_OHCI0_BASE,
> - Â Â Â [RSET_OHCI_PRIV] Â Â Â Â= BCM_6348_OHCI_PRIV_BASE,
> - Â Â Â [RSET_USBH_PRIV] Â Â Â Â= BCM_6348_USBH_PRIV_BASE,
> - Â Â Â [RSET_MPI] Â Â Â Â Â Â Â= BCM_6348_MPI_BASE,
> - Â Â Â [RSET_PCMCIA] Â Â Â Â Â = BCM_6348_PCMCIA_BASE,
> - Â Â Â [RSET_SDRAM] Â Â Â Â Â Â= BCM_6348_SDRAM_BASE,
> - Â Â Â [RSET_DSL] Â Â Â Â Â Â Â= BCM_6348_DSL_BASE,
> - Â Â Â [RSET_ENET0] Â Â Â Â Â Â= BCM_6348_ENET0_BASE,
> - Â Â Â [RSET_ENET1] Â Â Â Â Â Â= BCM_6348_ENET1_BASE,
> - Â Â Â [RSET_ENETDMA] Â Â Â Â Â= BCM_6348_ENETDMA_BASE,
> - Â Â Â [RSET_MEMC] Â Â Â Â Â Â = BCM_6348_MEMC_BASE,
> - Â Â Â [RSET_DDR] Â Â Â Â Â Â Â= BCM_6348_DDR_BASE,
> + Â Â Â __GEN_CPU_REGS_TABLE(6348)
> Â};
>
> Âstatic const int bcm96348_irqs[] = {
> - Â Â Â [IRQ_TIMER] Â Â Â Â Â Â = BCM_6348_TIMER_IRQ,
> - Â Â Â [IRQ_UART0] Â Â Â Â Â Â = BCM_6348_UART0_IRQ,
> - Â Â Â [IRQ_DSL] Â Â Â Â Â Â Â = BCM_6348_DSL_IRQ,
> - Â Â Â [IRQ_ENET0] Â Â Â Â Â Â = BCM_6348_ENET0_IRQ,
> - Â Â Â [IRQ_ENET1] Â Â Â Â Â Â = BCM_6348_ENET1_IRQ,
> - Â Â Â [IRQ_ENET_PHY] Â Â Â Â Â= BCM_6348_ENET_PHY_IRQ,
> - Â Â Â [IRQ_OHCI0] Â Â Â Â Â Â = BCM_6348_OHCI0_IRQ,
> - Â Â Â [IRQ_PCMCIA] Â Â Â Â Â Â= BCM_6348_PCMCIA_IRQ,
> - Â Â Â [IRQ_ENET0_RXDMA] Â Â Â = BCM_6348_ENET0_RXDMA_IRQ,
> - Â Â Â [IRQ_ENET0_TXDMA] Â Â Â = BCM_6348_ENET0_TXDMA_IRQ,
> - Â Â Â [IRQ_ENET1_RXDMA] Â Â Â = BCM_6348_ENET1_RXDMA_IRQ,
> - Â Â Â [IRQ_ENET1_TXDMA] Â Â Â = BCM_6348_ENET1_TXDMA_IRQ,
> - Â Â Â [IRQ_PCI] Â Â Â Â Â Â Â = BCM_6348_PCI_IRQ,
> + Â Â Â __GEN_CPU_IRQ_TABLE(6348)
> +
> Â};
>
> -/*
> - * 6358 register sets and irqs
> - */
Same comment comment.
Jonas
