> Hi, Adam > > On 8/28/10, Adam Jiang <jiang.adam@xxxxxxxxx> wrote: > > How dose interrupt be handled on SMP build on MIPS architecture? Does > > mips-linux support SMP? > > > > $ grep SYS_SUPPORTS_SMP -ur arch/mips/Kconfig | egrep -v "config|depend" | wc -l > 6 > > You can get more information from the book "See MIPS Run Linux" version 2. Thank you, Wu. I'd like to read the book ASAP. I have gotten a general image how multi-APIC system distribute IRQs to each CPU on x86 architecture. For misp, is there a mechanism to do the same thing? Another question is about the comments in file arch/mips/kernel/irq_cpu.c it is said "8 interrupt sources" things could not be applied to SMP. What dose this mean? How is MIPS CPU interrupts handled? Could I get a general information from MIPS programmer manual? Best regards, /Adam > > Regards, > Wu Zhangjin >
