Hi All,
I am getting a exception in board.c , at the end of serial_init function i.e. when i access to stack pointer (SP).
The return address register ra value is not correct.
I am porting U-boot-2010.03 for MIPS32 Au1350 processor.
board specs:-
CPU Frequency - 396 MHz
System Bus Frequency - 198 MHz
SDRAM (DDR2) Frequency - 198 MHz
SDRAM Base address is - 0x80000000
SP offset is - 0x400000
I am able to read and write DDR2 SDRAM from BDI3000, but how to check whether my DDR2 SDRAM Configuration is working or not from U-Boot.
below is the error log file:-
Au1350>bi 0xbfc195c0
Breakpoint identification is 0
Au1350>go
- TARGET: core #0 has entered debug mode
Au1350>info
Core number : 0
Core state : Debug Mode
Debug entry cause : exception
Current PC : 0xbfc195c0
Current SR : 0x00400000
Current LR (r31) : 0xbfc195bc
Current SP (r29) : 0x803fff90
Current EPC : 0x18222521
Au1350>ti
Core number : 0
Core state : Debug Mode
Debug entry cause : single step
Current PC : 0xbfc195c4
Current SR : 0x00400000
Current LR (r31) : 0x440c0050
Current SP (r29) : 0x803fff90
Au1350>ti
Core number : 0
Core state : Debug Mode
Debug entry cause : single step
Current PC : 0xbfc195c8
Current SR : 0x00400000
Current LR (r31) : 0x440c0050
Current SP (r29) : 0x803fff90
Au1350>ti
Core number : 0
Core state : Debug Mode
Debug entry cause : single step
Current PC : 0x440c0050
Current SR : 0x00400000
Current LR (r31) : 0x440c0050
Current SP (r29) : 0x803fffb0
Au1350>ti
Core number : 0
Core state : Debug Mode
Debug entry cause : single step
Current PC : 0xbfc00200
Current SR : 0x00400002
Current LR (r31) : 0x440c0050
Current SP (r29) : 0x803fffb0
Au1350>
please let me know whether SDRAM DDR2 configuration is wrong or am missing something. why am not able to access SP from U-boot.
Also SDRAM initialzation in YAMON and U-boot is totally different. please let me know which one is working fine.
With Thanks and Regards,
Gurumurthy Gowdar
KPIT Cummins Infosystems Pvt Ltd
