Hi, Ralf This one is urgent, could you please review it, thanks ;) Regards, Wu Zhangjin On Fri, 2010-05-07 at 00:59 +0800, Wu Zhangjin wrote: > The interrupt enable bit of performance counters of Loongson is in the > control register($24), not in the counter register, so, in > loongson2_perfcount_handler(), we need to use > > enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN; > > instead of > > enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; > > Reported-by: Xu Hengyang <hengyang@xxxxxxxxxxxxxxxx> > Signed-off-by: Wu Zhangjin <wuzhangjin@xxxxxxxxx> > --- > arch/mips/oprofile/op_model_loongson2.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c > index 29e2326..fa3bf66 100644 > --- a/arch/mips/oprofile/op_model_loongson2.c > +++ b/arch/mips/oprofile/op_model_loongson2.c > @@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) > */ > > /* Check whether the irq belongs to me */ > - enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; > + enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN; > if (!enabled) > return IRQ_NONE; > enabled = reg.cnt1_enabled | reg.cnt2_enabled;