On Wed, 05 May 2010 12:20:10 -0700, "Kevin D. Kissell" <kevink@xxxxxxxxxxxxx> wrote: > > Yes, that's my patch. Though I cannot remember precisely, maybe I > > just had (mis)thought Cause bits in FCSR are read-only at that time. > > I have never used real SMP MIPS platforms, so there must be no > > SMP-related issues. > > > The patch was labeled for "preemption and SMP problems", and if you > weren't working on an SMP system, I'd guess that you were working with > full preemption and seeing a problem that you might have assumed was > also relevant to SMP. The FPU emulator *shouldn't* have pre-emption > issues, since it works off of data structures that are instantiated per > thread context. The FCSR seen by thread A is logically independent of > that seen by thread B, so that even if one emulation was preempted in > the middle by another, they shouldn't be able to interfere with one > another. That was the concept, anyway. Yes, I created the patch for full preemption support. At that time, ieee754_csr was a global variable, not an alias of current->thread.fpu.soft.fcr31. The commmit 72402e was mixture of two patch: "just make FPU emulator fully-preemptive" and "fix FPU ownership issues on preemption". The wrong code is a part of the first one. So I don't think your fix causes any regressions on SMP/preemption point of view. I'm still trying to remember why I masked out some bits on CTC1 emulation, but no success. Maybe I was just confused. Anyway, thanks Shane and Kevin! --- Atsushi Nemoto
