On Wed, Jul 08, 2009 at 06:17:42PM +0530, joe seb wrote: > Hi, > > We made the following changes and tried, > > -> applied the patch given by you. > -> changed the PHYS_OFFSET to 0x10000000 to match our memory offset. > -> cache write back mode enabled > > Still we face the same problem. It crashes at different points when it > enters the user space. I have attached one of the logs. > > But in cache write through mode it works. Another thought: if it works with write through, but not write back, you may have a device driver that isn't flushing/invalidating cache appropriately before doing DMA. This is much more important on MIPS than many other processors. Is this a new platform or one that has been working for a while? David VomLehn
