On Wed, Jul 08, 2009 at 11:37:56AM +0100, Ralf Baechle wrote: > On Wed, Jul 08, 2009 at 01:37:42PM +0530, joe seb wrote: > > > We are trying to port linux 2.6.29.4 version of the kernel from > > linux-mips.org site to our MIPS 24K based platform and we see issues when we > > use the cache in write-back mode. Cache with write-through configuration > > works fine. ... > > CPU 0 Unable to handle kernel paging request at virtual address cccccccc, > > epc == > > cccccccc, ra == cccccccc ... > > We get crashes at different places and the above crash is one of them. > > Do you think this failure is due to the wrong cache configuration or related > > to the d-cache aliasing problem? In a narrow sense, when you get a page fault at an address that equals the value of the EPC register and the ra register is the same value, you have probably smashed your stack. Specifically, you smashed the location where the ra value was stored on function entry. When you restored it to ra and did a jr ra, you put the value in the pc register. One possible cause is a stack overflow. This is unlikely, but I've seen drivers put big enough buffers on the stack that it intruded into the thread_info area. This causes all sorts of badness to happen. > (Why do people use non-zero starting addresses for memory? Handling of > cache error exceptions is hard enough as it is but with no memory in the > low 32k the design idea of the cache architecture that stores relative to > $zero can be used goes down the drain and (not considering platform-specific > solutions here) only be handled by burning the scarce resource of a TLB > entry for an extremly rare event ...) (Because hardware people are, uh, insufficiently acquainted with the MIPS architecture and don't know what the conventions are. Or why they are that way. Then, you're stuck with that architecture forever. Sigh.) > Ralf David VomLehn
