On Tue, Jan 08, 2008 at 06:02:06PM +0100, Thomas Bogendoerfer wrote: > On Wed, Jan 09, 2008 at 12:35:06AM +0800, lovecentry wrote: > > As we know in mips achitecture if current pc falls into kseg1 segment, any > > memory reference will bypass cache and fetch directly from dram. But for > > some prcoessor such like mips R10K it has off chip L2 cache. I haven't found > > why do you think so ? R10k L2 cache controller is inside CPU and any > access with uncached attribute will go directly to memory. The only > systems, where this might be different are systems with caches unknown > to the cpu. But even those usually obey that uncached accesses are > going directly to memory. It should also be mentioned that some R10000 machines do odd stuff with uncached addresses. IP27 class machines reuse the entire physical address space several times to map different things. The selection of the four uncached address spaces id done by the uncached attribute which is specified either in the TLB or or as as bit 59..60 of a virtual address in XKPHYS. The memory controller of the Indigo 2 R10000 needs to be switched to a special slower mode to allow uncached accesses first. Ralf
