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Hi As we know in mips
achitecture if current pc falls into kseg1 segment, any memory reference will
bypass cache and fetch directly from dram. But for some prcoessor such like
mips R10K it has off chip L2 cache. I haven't found any available path which
can access dram directly. All memory reference need pass through L2 cache. Does
it mean any memory reference in kseg1 will be fetch from L2 cache rather than
dram for such system? How does such system design when system software need
access kseg1 region? Further more, Kseg2 is used to do memory map for those peripheral
so Is there has a particular circuit that routes those access to the appropriate
destination. Any suggestion is
highly appreciate!!! Tony |
