On Wed, Jan 09, 2008 at 12:35:06AM +0800, lovecentry wrote: > As we know in mips achitecture if current pc falls into kseg1 segment, any > memory reference will bypass cache and fetch directly from dram. But for > some prcoessor such like mips R10K it has off chip L2 cache. I haven't found why do you think so ? R10k L2 cache controller is inside CPU and any access with uncached attribute will go directly to memory. The only systems, where this might be different are systems with caches unknown to the cpu. But even those usually obey that uncached accesses are going directly to memory. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ]
