I did a bit more work and investigation on this and it turns out I could not read the mmio in kernel space because I had not done a pci_enable_device_bars() on the device. I had never done this on x86 so I didn't realize it was necessary. > The virtual address 0xc0300000 looks sensible and the physical address > 0x24000000 is consistent with what you found in the BAR registers. So that > all looks reasonable but that only means not obviously wrong. So next I > wonder what the value of PCI_MMIO_BASE is ... The PCI_MMIO_BASE is a defined as: > #define PCI_MMIO_BASE (0x00040000) This is define in the technical documentation as the offset to access pci config space from the mmio. I am using this because I know what the values should be so it provides a nice sanity check. > A bus error is an exception which is signalled by agent external (often > called system controller) to the CPU core to signal a fatal error during a > read or write bus transaction, for example after a bus timeout or if the > address of the read/write isn't assigned to any device. PCI master abort > also is often mapped to a bus error exception. So after doing pci_enable_bars() I can now access this mmio region in kernel space. However, if I try to mmap this into user space I still receive the bus error. I am mapping this into user space using the example for LDD which says to use the remap_pfn_range() function. I've tested this on the x86 and it works as expected, however every time I access the mmio from user space using the mips, I continue to get the bus error I previously received in kernel space. Any idea what I might be doing wrong? How can I access this from user space? Thanks, Jon
