On Fri, Aug 03, 2007 at 12:59:41PM +0200, Mohamed Bamakhrama wrote: > Hi all, > I have one question regarding context switches between user and kernel > modes and interrupts. Do they invalidate the I-cache or D-cache? Never on MIPS. I call an architecture that would require a cacheflush for such a context switch totally broken and yes, they exist - but nothing from the MIPS family. Ralf
