On Oct 10, 2006, at 3:41 PM, Sergei Shtylyov wrote:
Note that AMD claims that the latency (and other) errata fixed
in the late revs of their SOCs.
For Au1100, BE and BF revs are claimed to be errata-free.
I've been looking for the code I did long ago for
this, but haven't found it yet. As I recall, the BE and
later version actually fixed some chip bugs, but didn't
solve the design challenges of the CPU responding
in a required time to collect proper status or to
meet the USB timing.
I'll keep looking and do whatever I can to help out.
Thanks.
-- Dan
