On Tue, 3 Feb 2004, Ralf Baechle wrote: > I don't know details but since the person who answered my question was > directly working on the CPU design I have to take that as authoritative > information and after all, the systems seems stable. OK then. > Daring a guess, the CPU restarts the pipeline following an eret therefore > instructions preceeding the eret can't cause the problem. That's possible. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
