Gareth wrote: > Hi, > > I have been going through my mips architecture book learning about the delay > slots used in loads, jumps and branches and I am in need of some clarification. > The instruction just after the jump instruction is always executed wether the > jump is taken or not, right? There are no conditional jumps, so you are right. :-) > So the compiler can re-aarange the assembly to > take advantage of this, but if no instruction (that can be executed wether the > jump is taken or not) can be placed after the jump, a nop is used intstead. So > take this code for example : > > jal <my_function> > li $s2, 3 > li $v0, 2 The register name is either "$2" or "v0". > If the jump is not taken, it requires 3 cycles to execute these 3 instructions. > If the jump is taken, it requires 3 cycles to execute the first instruction of > my_function, and li $s2, 3 is executed. > > Is my reasoning correct? Yes, if it was e.g. beq t0, zero, <my_function> instead of jal. Note that the "branch likely" variants don't execute the delay slot if not taken. Thiemo
