On Tue, Aug 20, 2002 at 03:55:34PM +0200, Maciej W. Rozycki wrote: > An additional thought that just came to my mind: it might be possible to > avoid masking interrupts with a dummy ll/sc pair only checking if an > interrupt happened within the critical code. It should be easy to > validate since only a single mask of a processor would make use of the > code. The real question is: "Do the affected cache operations corrupt any > state or do they only work on wrong lines?" If the latter, the approach > should work for all operations except from "Hit_Invalidate_D" that > corrupts state by definition (but it isn't used by any R4k processor, so > it may simply be replaced with a panic()). Unfortunately, the knowledge > does no longer exist within IDT, but maybe someone else knows? I was thinking about that already but the erratas don't provide enough details. The only problem I can see is that ll/sc are fairly slow on some architectures. They're supposed to be quite light according to the docs but in reality I benchmarked ~ 13 cycles for a spinlock on a R10000 and ~ 44 on a more recent chip. Ralf
