On Tue, 20 Aug 2002, Ralf Baechle wrote: > I was thinking about that already but the erratas don't provide enough > details. The only problem I can see is that ll/sc are fairly slow on some Well, IDT didn't seem much mobilized with my single query. Maybe if there was more interest expressed, someone would go digging through old resources for real. > architectures. They're supposed to be quite light according to the docs > but in reality I benchmarked ~ 13 cycles for a spinlock on a R10000 and > ~ 44 on a more recent chip. Well, the code would only execute on an R4600 V1.7... -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
