Carsten Langgaard wrote: > > Unfortunately, it's required by manuals for some processors. As I know, > > IDT HW manuals clearly state cache flush routines must operate from > > uncached code and must access uncached data only. Examples are R30x1 CPU > > series. > > Yes, that's true. > But that code belongs in the R30xx specific cache routines, not in the MIPS32 cache > routines. I don't wonder if other IDT CPUs also require this, including those that conform MIPS32. Basically, requirement of uncached run makes hadrware logic much simpler and allows to save silicon a bit. Regards, Gleb.
