"Gleb O. Raiko" wrote: > Carsten Langgaard wrote: > > > Unfortunately, it's required by manuals for some processors. As I know, > > > IDT HW manuals clearly state cache flush routines must operate from > > > uncached code and must access uncached data only. Examples are R30x1 CPU > > > series. > > > > Yes, that's true. > > But that code belongs in the R30xx specific cache routines, not in the MIPS32 cache > > routines. > > I don't wonder if other IDT CPUs also require this, including those that > conform MIPS32. > Basically, requirement of uncached run makes hadrware logic much simpler > and allows to save silicon a bit. That could be true, but then again I suggest making specific cache routines for those CPUs. It would be a real performance hit for the rest of us, if we have to operate from uncached space. > > Regards, > Gleb. -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com
