On Mon, 18 Feb 2002, Hartvig Ekner wrote: > You are no doubt correct regarding the R4K manual - so my comment probably > only applies for CPU's that claim to be MIPS32/MIPS64 compliant. All MTI's > CPU offerings (cores only) do in fact flush the WB on a SYNC to comply with > the current spec. Note that the MIPS II spec doesn't forbid a "sync" implementation to be stronger than required. > This I do have a problem understanding. If the SYNC does not flush the WB > on some processor/writebuffer combinations, and a read can be satisfied > out of the WB, how would you ever be able to guarantee that DMA data written > by the CPU has reached memory before triggering the IO device? If after a "sync" an uncached read could be satisfied from an uncommittedd write pending since before the "sync" in a CPU's oncore WB, then the CPU would violate the MIPS II spec of "sync", as the order of transactions at this CPU's external bus would not be preserved. You may exploit this property to do a write-back flush to the host bus -- that's what I added iob() for. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
