Maciej W. Rozycki writes: > > On Fri, 15 Feb 2002, Hartvig Ekner wrote: > > > But in-order for the CPU is not enough - it also needs to make sure all > > written data is visible for DMA accesses to memory from the outside, which > > is why the writebuffer needs to be flushed by a SYNC as well. From the > > definition of "SYNC": > > > > "A store is completed when the stored value is visible to every other > > processor in the system". > > > > Which presumably also includes DMA I/O devices... > > The description found in the R4k manual seems to contradict. A "sync" on > a single CPU only assures transactions on it's external bus will happen in > order wrt the "sync". In a multiple-CPU environment all CPUs interested > in a barrier need to execute a "sync". That's seems natural -- how would > you define a synchronization point for a CPU that does not execute a > "sync". You are no doubt correct regarding the R4K manual - so my comment probably only applies for CPU's that claim to be MIPS32/MIPS64 compliant. All MTI's CPU offerings (cores only) do in fact flush the WB on a SYNC to comply with the current spec. > Since I/O devices have no means to signal a CPU a "sync" operation, how > can you expect a "sync" on the CPU to complete all preceding writes to the > device? It's only a following read that may imply it. This I do have a problem understanding. If the SYNC does not flush the WB on some processor/writebuffer combinations, and a read can be satisfied out of the WB, how would you ever be able to guarantee that DMA data written by the CPU has reached memory before triggering the IO device? /Hartvig > > -- > + Maciej W. Rozycki, Technical University of Gdansk, Poland + > +--------------------------------------------------------------+ > + e-mail: macro@ds2.pg.gda.pl, PGP key available + > > -- _ _ _____ ____ Hartvig Ekner Mailto:hartvige@mips.com |\ /| | |____)(____ Direct: +45 4486 5503 | \/ | | | _____) MIPS Denmark Switch: +45 4486 5555 T E C H N O L O G I E S http://www.mips.com Fax...: +45 4486 5556
