On Sun, 1 Sep 2002, Mark D. Studebaker wrote: > Ky?sti M?lkki wrote: > > > Two successive Write Quick "0" become Write Byte, only changing the > > reference for Read Byte transactions. This is i2cdetect operation and > > causes no corruption. > > > It also means 2 x Write Quick would reset the state machine and prevent > > corruption... > > So if we add a second Write Quick "0" - only in the range 54-57 is > necessary - that sounds like a good fix. Agreed? That's good first aid. To be Really Safe (TM), one must not release adapter lock in between. EEPs could still corrupt if you have a sensor module loaded and you run i2cdetect. Also sensor clients' attach_adapter uses Write Quick, often followed by Read Byte Data. Currently only eeprom.o is left in the mentioned range. So maybe i2c-core deserves an option of doubling, preventing or faking Write Quick's in the range. I don't know about SMBus, but i2c defines multi-master topology. Unless we can force SCL low between the two Quicks, some embedded controller can still screw things up for us. -- Ky?sti M?lkki kmalkki at cc.hut.fi
