On Mon, Jul 26, 2010 at 3:33 PM, Matthew Garrett <mjg59@xxxxxxxxxxxxx> wrote: > On Mon, Jul 26, 2010 at 03:31:28PM -0700, Luis R. Rodriguez wrote: >> On Mon, Jul 26, 2010 at 3:29 PM, Matthew Garrett <mjg59@xxxxxxxxxxxxx> wrote: >> > On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote: >> > >> >> What I meant was that the PCI config space would already have L1 >> >> enabled if L1 worked, so I don't see why we would need to nitpick out >> >> specifics here. All Atheros PCIE chips should work with L1. The advise >> >> given is to disable L0s though. I believe AR2425 would be one which >> >> likely had L0s enabled but requires it to be disabled. Not sure of >> >> others. But this is why I am saying this can be done globally for all >> >> ath5k chipsets. >> > >> > If L1 is set but the chip is pre-PCIe 1.1 then we'll disable L1 unless >> > the driver tells us that it's functional. The .inf from the Windows >> > driver seemed to suggest that only a subset of the chips re-enabled L1 >> > there, but if it's ok in general then that's a straightforward one-line >> > patch. >> >> But why can't we just rely on what the device already has on its PCI >> config space and only ensure to disable L0s? > > Because we globally disable ASPM on pre-1.1 devices, because that's what > Windows does. It makes it easier for us to figure out what level of > support we can expect from different hardware revisions. I see.. thanks Mathew... in that case since L1 works on all devices we could just force enable L1 for all PCIE devices. What do you think? Luis -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
