On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote: > What I meant was that the PCI config space would already have L1 > enabled if L1 worked, so I don't see why we would need to nitpick out > specifics here. All Atheros PCIE chips should work with L1. The advise > given is to disable L0s though. I believe AR2425 would be one which > likely had L0s enabled but requires it to be disabled. Not sure of > others. But this is why I am saying this can be done globally for all > ath5k chipsets. If L1 is set but the chip is pre-PCIe 1.1 then we'll disable L1 unless the driver tells us that it's functional. The .inf from the Windows driver seemed to suggest that only a subset of the chips re-enabled L1 there, but if it's ok in general then that's a straightforward one-line patch. -- Matthew Garrett | mjg59@xxxxxxxxxxxxx -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
