2010/4/11 Sujith <Sujith.Manoharan@xxxxxxxxxxx>: > tom.leiming@xxxxxxxxx wrote: >> In ath9k_hif_usb_alloc_rx_urbs, ath9k-htc will pass skb->data into >> usb hcd and usb hcd will do dma mapping and unmapping to the buffer >> pointed by skb->data, so we should pass a cache-line aligned address. >> >> This patch replace __dev_alloc_skb with alloc_skb to make skb->data >> pointed to a cacheline aligned address simply since ath9k-htc does not >> skb_push on the skb. >> > > AFAIK, the only architecture that has a requirement to override NET_SKB_PAD > is powerpc, and it does it anyway - by setting it to a cacheline size. > > So why do we need to do this ? Documentation/DMA-API.txt says: | Warnings: Memory coherency operates at a granularity called the cache | line width. In order for memory mapped by this API to operate | correctly, the mapped region must begin exactly on a cache line | boundary and end exactly on one (to prevent two separately mapped | regions from sharing a single cache line). Since the cache line size | may not be known at compile time, the API will not enforce this | requirement. Therefore, it is recommended that driver writers who | don't take special care to determine the cache line size at run time | only map virtual regions that begin and end on page boundaries (which | are guaranteed also to be cache line boundaries) The skb->data is passed into usb hcd and usb hcd will do dma mapping for the buffer of skb->data, so it is better to keep it cache-line aligned. Size of cache line is very cpu dependent, we can't suppose it is 32byte(NET_SKB_PAD) aligned, 64byte or more is very possible. Thanks, -- Lei Ming -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
