Hi Linus,
Please pull from 'master' branch of
git://www.linux-watchdog.org/linux-watchdog.git
It will fix the watchdog mask bit offset for Exynos7.
This will update the following files:
s3c2410_wdt.c | 2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
with these Changes:
commit 5476b2b77dae50c88aa6a85f21abeac38dde590f
Author: Abhilash Kesavan <a.kesavan@xxxxxxxxxxx>
Date: Fri Oct 17 21:42:53 2014 +0530
watchdog: s3c2410_wdt: Fix the mask bit offset for Exynos7
The watchdog mask bit offset listed for Exynos7 is incorrect.
Fix this.
Signed-off-by: Abhilash Kesavan <a.kesavan@xxxxxxxxxxx>
Acked-by: Naveen Krishna Chatradhi <naveenkrishna.ch@xxxxxxxxx
Reviewd-by: Guenter Roeck <linux@xxxxxxxxxxxx>
Signed-off-by: Wim Van Sebroeck <wim@xxxxxxxxx>
For completeness, I added the overal diff below.
Greetings,
Wim.
================================================================================
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 8532c3e..1626dc6 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -161,7 +161,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
static const struct s3c2410_wdt_variant drv_data_exynos7 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
- .mask_bit = 0,
+ .mask_bit = 23,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 23, /* A57 WDTRESET */
.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
--
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