For calculating FIFO offsets, the sizes of preceding fifos need to be
known. For filling the GDFIFOCFG register, these fifo sizes were read
from hardware registers. However, these values were written to these
registers just a few lines before, so we can just use the values written
instead.
Signed-off-by: Matthijs Kooijman <matthijs@xxxxxxxx>
---
drivers/staging/dwc2/core.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
If there is some scenario possible where the FIFO size values written to
these registers are not actually applied, this patch could cause a
problem. However, given the fact that the fifo size values are validated
against the maximum values read from the hardware, this should be ok?
diff --git a/drivers/staging/dwc2/core.c b/drivers/staging/dwc2/core.c
index 07f91e6..cc2431f 100644
--- a/drivers/staging/dwc2/core.c
+++ b/drivers/staging/dwc2/core.c
@@ -499,7 +499,7 @@ void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *params = hsotg->core_params;
- u32 rxfsiz, nptxfsiz, hptxfsiz, dfifocfg;
+ u32 nptxfsiz, hptxfsiz, dfifocfg;
if (!params->enable_dynamic_fifo)
return;
@@ -547,11 +547,10 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
* include RxFIFO, NPTXFIFO and HPTXFIFO
*/
dfifocfg = readl(hsotg->regs + GDFIFOCFG);
- rxfsiz = readl(hsotg->regs + GRXFSIZ) & 0x0000ffff;
- nptxfsiz = readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
- hptxfsiz = readl(hsotg->regs + HPTXFSIZ) >> 16 & 0xffff;
dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
- dfifocfg |= (rxfsiz + nptxfsiz + hptxfsiz) <<
+ dfifocfg |= (params->host_rx_fifo_size +
+ params->host_nperio_tx_fifo_size +
+ params->host_perio_tx_fifo_size) <<
GDFIFOCFG_EPINFOBASE_SHIFT &
GDFIFOCFG_EPINFOBASE_MASK;
writel(dfifocfg, hsotg->regs + GDFIFOCFG);
--
1.8.0
--
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