Chen Peter-B29397 <B29397@xxxxxxxxxxxxx> writes: > >> > >> Yes but the current hostpc code does 3 things today on Linux : >> * different reset (ehci-hcd) >> * different speed detection (ehci-hub) >> * managing of power of phy (ehci-hub) with PHCD bit >> >> But the PHCD bit already exist in pre-lpm chipidea core. It is located on >> port register [1]. >> So I think the low power phy code can be used on pre-lpm core. >> >> The hostpc register only exist because with lpm, the hacked reserved >> field in port register weren't available anymore : >> ehci with lpm : >> #define PORT_LPM (1<<9) /* LPM transaction */ >> #define PORT_DEV_ADDR (0x7f<<25) /* device address */ >> #define PORT_SSTS (0x3<<23) /* suspend status */ >> >> chipidea without lpm >> 9 HSP (high speed status) >> 23 PHCD (phy clock disable) >> 24 PFSC (force speed) >> 26-27 (port speed) >> >> The strange things about hostpc register is that they didn't keep the >> same mapping (shift by 1): >> #define HOSTPC_PHCD (1<<22) /* Phy clock disable */ >> #define HOSTPC_PSPD (3<<25) /* Port speed detection */ >> >> I have patches to try cleaning that (separate hostpc stuff from phy clock >> disable). >> >> Peter do you know if all chipidea core have the PHCD bit in port >> register ? >> > The datasheet on my hand is CI13320A, and there are no hostpc and lpm support. > And there is PHCD bit at the 23th bit at portsc. My understanding is that this is true for non lpm-capable devices. In lpm-capable devices, PHCD is, like Matthieu said, 22nd bit of hostpc. Non lpm-capable devices don't have hostpc or devlc. Regards, -- Alex -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
