RE: [PATCH v8 15/20] usb: chipidea: add host role

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> be
> >> replaced with ehci_is_TDI(ehci) && HCC_LPM(hcc_params) ?
> >
> > Well, that's pretty much how it ends up in the chipidea code, I set
> > has_hostpc from the lpm flag, which is read from HCCPARAMS in the
> > driver's probe. I'm about to resend the patchset with this change.
> >
> >> - fix tdi_reset and tdi_in_host_mode to use the correct register
> (USBMODE or
> >> USBMODE_EX according to has_hostpc). May be we should move the code [1]
> in
> >> tdi_reset ?
> >
> > Sounds sensible to me. At least it will make the code a bit more
> > understandable. But I'd like to do this outside of the chipidea
> patchset
> > (since the tdi_reset() currently does no harm).
> >
> >> Is there a public datasheet to lpm chipidea controller ?
> >
> > Unfortunately, I don't really know. I suspect not.
> 
> Ok, not lpm version of chipidea core got also PHCD bit for controlling
> "PHY Low
> Power" [1]
> 
> Do you know if the hostpc code in ehci-hub can also be used for those
> controller
> (minus the different register mapping) ?
> 
I think chipidea core has no hostpc register, 
host pc extension is introduced by 331ac6b2, and used for Intel Moorestown
EHCI controller. 

And I think there may be not lpm chipidea controller.

So has_hostpc and has_lpm should be both 0 for chipidea core.
> 
> [1]
> see http://www.nxp.com/documents/user_manual/UM10314.pdf p130
> 
> PHCD   PHY low power suspend - clock disable (PLPSCD)
>    R/W 0
>        In host mode, the PHY can be put into Low Power Suspend  Clock
>        Disable when the downstream device has been put into suspend mode
> or
>        when no downstream device is connected. Low power suspend is
>        completely under the control of software.
>      1 Writing a 1 disables the PHY clock. Reading a 1 indicates the
> status of the
>        PHY clock (disabled).
>      0 Writing a 0 enables the PHY clock. Reading a 0 indicates the
> status of the
>        PHY clock (enabled).


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