> > Do you know if the hostpc code in ehci-hub can also be used for > > those controller > > (minus the different register mapping) ? > > > I think chipidea core has no hostpc register, > host pc extension is introduced by 331ac6b2, and used for Intel > Moorestown EHCI controller. > Yes but the current hostpc code does 3 things today on Linux : * different reset (ehci-hcd) * different speed detection (ehci-hub) * managing of power of phy (ehci-hub) with PHCD bit But the PHCD bit already exist in pre-lpm chipidea core. It is located on port register [1]. So I think the low power phy code can be used on pre-lpm core. The hostpc register only exist because with lpm, the hacked reserved field in port register weren't available anymore : ehci with lpm : #define PORT_LPM (1<<9) /* LPM transaction */ #define PORT_DEV_ADDR (0x7f<<25) /* device address */ #define PORT_SSTS (0x3<<23) /* suspend status */ chipidea without lpm 9 HSP (high speed status) 23 PHCD (phy clock disable) 24 PFSC (force speed) 26-27 (port speed) The strange things about hostpc register is that they didn't keep the same mapping (shift by 1): #define HOSTPC_PHCD (1<<22) /* Phy clock disable */ #define HOSTPC_PSPD (3<<25) /* Port speed detection */ I have patches to try cleaning that (separate hostpc stuff from phy clock disable). Peter do you know if all chipidea core have the PHCD bit in port register ? > And I think there may be not lpm chipidea controller. Why ? The HOSTPC register is the CAP_DEVLC register we can found in ci13xxx_udc.c. #define CAP_DEVLC (0x084UL) #define DEVLC_PSPD (0x03UL << 25) > > So has_hostpc and has_lpm should be both 0 for chipidea core. > > > > [1] > > see http://www.nxp.com/documents/user_manual/UM10314.pdf p130 > > > > PHCD PHY low power suspend - clock disable (PLPSCD) > > R/W 0 > > In host mode, the PHY can be put into Low Power Suspend > > Clock Disable when the downstream device has been put into suspend > > mode or > > when no downstream device is connected. Low power suspend is > > completely under the control of software. > > 1 Writing a 1 disables the PHY clock. Reading a 1 indicates the > > status of the > > PHY clock (disabled). > > 0 Writing a 0 enables the PHY clock. Reading a 0 indicates the > > status of the > > PHY clock (enabled). > -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
