Hi, On Mon, Feb 06, 2012 at 02:18:08PM +0100, Sebastian Andrzej Siewior wrote: > >> it in detail but does dwc3_trb point directly into memory which accessed > >> by dwc3? If so it has to be __l32 and not u32 and you have to use proper > >> le32_to_cpu() macros and those for the other way around. > > > >Is it really needed now that I'm using play bitshifts ? The IP will be > >running at the same endianness as the cpu, no ? > > That is tricky. Take a look at ch 6.19. > Assume that your pci-e is stuffed into a powerpc. So once you prepare > the TRB & such in memory they end up BE in host memory. The dwc3 will > grab via PCIE and expect little endian format. So this is broken. > However you have a DWC_USB3_GSBU register which you could set to 1 in > such case. If this works well then you _could_ leave all descriptors in > host-native mode. Only register access will remain in LE mode. To avoid > confusion for the TRB descriptors (event buffers probably as well) I > would denote it as such. I'm not sure we will have such problems, I can update the commit log, but if someone wants to use this in BE, they cannot be penalized with a le32_to_cpu() everytime they want to do anything with the TRBs, because they can just set bit 12 of GSBUSCFG0 and the HW will start working in BE mode. At some point we could just add a couple of DT attributes for platforms to pass the desired SoC Bus mode down to driver via DT. What do you want me to add on commit log ? -- balbi
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