Re: [PATCHv7 00/19] First round in OTG rework

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Hi,

On Tue, Nov 29, 2011 at 01:42:56PM +0100, Matthieu CASTET wrote:
> > My goal on top of have the PHY split from OTG, is to have generic OTG
> > stage machine as part of the OTG utility. This would be useful
> > initially with the various ChipIdea UDC drivers that all seem to have
> > the OTG state machine implemented separately, the Marvell one being
> > the last to do this. The idea is to implement support for this generic
> > state machine for the ci13xxx_udc, that we are planning to make the
> > only driver for all the users of the ChipIdea UDC.
> 
> Are you planning to improve ci13xxx_udc ?
> AFAIK ci13xxx_udc lacks some features that are implemented by other drivers.
> For example the fsl one handle endianness.

There were couple of reasons why we started looking at ci13xxx_udc. I
just liked the name :). It's referring to the USB IP and not to a
platform. Alexander Shishkin is looking at the drivers, so he should
answer to this one. I think we need to start separate discussion about
this work. There have now been many guys interested in this, which is
nice, as this really needs to be done already.

> Also it could be interesting to benchmark all the existing drivers to see which
> one is better. In the old days ci13xxx_udc was very slow.

Alexander did test that langwell_udc is much faster, so if we continue
to use ci13xxx_udc, there is a whole lot of optimization to do, but
this will require a lot of work in any case.

> Also don't forget that there are different version of the core. For example
> ci13xxx_udc doesn't support older core that doesn't have USBADRA. See
> http://marc.info/?l=linux-usb&m=129906859817430&w=2

It may be that ci13xxx_udc is the wrong choice.

Thanks,

-- 
heikki
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