Re: [PATCHv7 00/19] First round in OTG rework

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Hi,

Heikki Krogerus a écrit :
> Hi,
> 

> My goal on top of have the PHY split from OTG, is to have generic OTG
> stage machine as part of the OTG utility. This would be useful
> initially with the various ChipIdea UDC drivers that all seem to have
> the OTG state machine implemented separately, the Marvell one being
> the last to do this. The idea is to implement support for this generic
> state machine for the ci13xxx_udc, that we are planning to make the
> only driver for all the users of the ChipIdea UDC.

Are you planning to improve ci13xxx_udc ?
AFAIK ci13xxx_udc lacks some features that are implemented by other drivers.
For example the fsl one handle endianness.

Also it could be interesting to benchmark all the existing drivers to see which
one is better. In the old days ci13xxx_udc was very slow.


Also don't forget that there are different version of the core. For example
ci13xxx_udc doesn't support older core that doesn't have USBADRA. See
http://marc.info/?l=linux-usb&m=129906859817430&w=2


Matthieu


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