<tmarri@...> writes:
> From: Tirumala Marri <tmarri-qTEPVZfXA3Y <at> public.gmane.org>
<snip>
> +/**
> + * This function modifies bit values in a register. Using the
> + * algorithm: (reg_contents & ~clear_mask) | set_mask.
> + */
> +static inline
> + void dwc_reg_modify(ulong reg, u32 offset, const u32 _clear_mask, const u32
_set_mask)
Strange indentation here. Also, you violate the 80-column limit here and
in other places as well. I guess you didn't run these patches through checkpatch?
> +{
> +#ifdef CONFIG_DWC_OTG_REG_LE
> + out_le32((unsigned __iomem *)(reg + offset),
> + (in_le32((unsigned __iomem *)(reg + offset)) & ~_clear_mask) |
> + _set_mask);
> +#else
> + out_be32((unsigned __iomem *)(reg + offset),
> + (in_be32(((unsigned __iomem *))(reg + offset)) & ~_clear_mask) |
> + _set_mask);
> +#endif
> +};
Here you do a read-modify-write sequence to an IO address. Are you
sure this function is always called from interrupt context / with the
appropriate lock held? Otherwise e.g. an interrupt handler might run
in the middle between the read and the write, and try to modify the
same register.
--
Paul
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