On Fri, Oct 7, 2011 at 8:00 AM, <tmarri@xxxxxxx> wrote:
> From: Tirumala Marri <tmarri@xxxxxxx>
>
[...]
> + * Do core a soft reset of the core. Be careful with this because it
> + * resets all the internal state machines of the core.
> + */
> +static void dwc_otg_core_reset(struct core_if *core_if)
> +{
> + ulong global_regs = core_if->core_global_regs;
> + u32 greset = 0;
> + int count = 0;
> +
> + /* Wait for AHB master IDLE state. */
> + do {
> + udelay(10);
> + greset = dwc_reg_read(global_regs, DWC_GRSTCTL);
> + if (++count > 100000) {
> + pr_warning("%s() HANG! AHB Idle GRSTCTL=%0x\n",
> + __func__, greset);
> + return;
> + }
> + } while (greset & DWC_RSTCTL_AHB_IDLE);
As per sepcs:
Bit 31: AHB Master Idle (AHBIdle): Indicates that the AHB Master State
Machine is in the IDLE condition.
So when this bit is 1 , AHB would be idle. So, what do you want here?
If AHB is idle, control wil return from above loop rather going ahead to execute
this function.
> +
> + /* Core Soft Reset */
> + count = 0;
> + greset |= DWC_RSTCTL_SFT_RST;
[...]
> + /* Rx FIFO */
> + dwc_reg_write(regs, DWC_GRXFSIZ, params->dev_rx_fifo_size);
> +
> + /* Set Periodic and Non-periodic Tx FIFO Mask bits to all 0 */
> + core_if->p_tx_msk = 0;
> + core_if->tx_msk = 0;
> +
> + if (core_if->en_multiple_tx_fifo == 0) {
> + /* Non-periodic Tx FIFO */
> + nptxsize = DWC_RX_FIFO_DEPTH_WR(nptxsize,
> + params->
> + dev_nperio_tx_fifo_size);
So, if you will follow the commnet of patch 01 then , here two you will have to
rename as TX_FIFO.
Also, at all other occurances.
> + nptxsize =
> + DWC_RX_FIFO_START_ADDR_WR(nptxsize,
> + params->dev_rx_fifo_size);
> + dwc_reg_write(regs, DWC_GNPTXFSIZ, nptxsize);
> +
> + ptxsize = DWC_RX_FIFO_START_ADDR_WR(ptxsize,
> + (DWC_RX_FIFO_START_ADDR_RD
> + (nptxsize) +
> + DWC_RX_FIFO_DEPTH_RD
> + (nptxsize)));
> + for (i = 0;
> + i < DWC_HWCFG4_NUM_DEV_PERIO_IN_EP_RD(core_if->hwcfg4);
> + i++) {
Reading hwcfg4 will give you maximum nuber of fifos provided by hardware.
But, a particular application (platform) may not need all those fifo. Since, you
have a vriable fifo_num in your param list, so why not use that?
> + ptxsize =
> + DWC_RX_FIFO_DEPTH_WR(ptxsize,
> + params->
> + dev_perio_tx_fifo_size[i]);
> + dwc_reg_write(regs, DWC_DPTX_FSIZ_DIPTXF(i), ptxsize);
> + ptxsize = DWC_RX_FIFO_START_ADDR_WR(ptxsize,
> + (DWC_RX_FIFO_START_ADDR_RD
> + (ptxsize) +
> + DWC_RX_FIFO_DEPTH_RD
> + (ptxsize)));
> + }
> + } else {
> + nptxsize = DWC_RX_FIFO_DEPTH_WR(nptxsize,
> + params->
> + dev_nperio_tx_fifo_size);
> + nptxsize =
> + DWC_RX_FIFO_START_ADDR_WR(nptxsize,
> + params->dev_rx_fifo_size);
> + dwc_reg_write(regs, DWC_GNPTXFSIZ, nptxsize);
> +
> + txsize = DWC_RX_FIFO_START_ADDR_WR(txsize,
> + (DWC_RX_FIFO_START_ADDR_RD
> + (nptxsize) +
> + DWC_RX_FIFO_DEPTH_RD
> + (nptxsize)));
> + for (i = 1;
> + i < DWC_HWCFG4_NUM_DEV_PERIO_IN_EP_RD(core_if->hwcfg4);
> + i++) {
Same as above
> + txsize =
> + DWC_RX_FIFO_DEPTH_WR(txsize,
> + params->dev_tx_fifo_size[i]);
> + dwc_reg_write(regs, DWC_DPTX_FSIZ_DIPTXF(i - 1), txsize);
> + txsize = DWC_RX_FIFO_START_ADDR_WR(txsize,
> + (DWC_RX_FIFO_START_ADDR_RD
> + (txsize) +
> + DWC_RX_FIFO_DEPTH_RD
> + (txsize)));
> + }
> + }
> +}
> +
Regards
Pratyush
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