From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
BUSWAIT is a 4-bit-wide value that controls the number of access waits
from the CPU to on-chip USB module. b'0000 inserts 0 wait (2 access
cycles) and b'1111 inserts 15 waits (17 access cycles, hardware
initial value), respectively.
BUSWAIT value depends on peripheral clock frequency supplied to on-chip
of each CPU, hence should be configurable through platform data.
Note that this patch assumes that b'0000 (0 wait, 2 access cycles) is
rerely used and considered as invalid. If valid 'buswait' data is not
provided by platform, initial b'1111 (15 waits, 17 access cycles) will
be applied as a safe default.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Signed-off-by: Felipe Balbi <balbi@xxxxxx>
---
drivers/usb/gadget/r8a66597-udc.c | 6 +++++-
include/linux/usb/r8a66597.h | 3 +++
2 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c
index 4f3f1ce..834a020 100644
--- a/drivers/usb/gadget/r8a66597-udc.c
+++ b/drivers/usb/gadget/r8a66597-udc.c
@@ -576,7 +576,11 @@ static void init_controller(struct r8a66597 *r8a66597)
u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
if (r8a66597->pdata->on_chip) {
- r8a66597_bset(r8a66597, 0x04, SYSCFG1);
+ if (r8a66597->pdata->buswait)
+ r8a66597_write(r8a66597, r8a66597->pdata->buswait,
+ SYSCFG1);
+ else
+ r8a66597_write(r8a66597, 0x0f, SYSCFG1);
r8a66597_bset(r8a66597, HSE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
diff --git a/include/linux/usb/r8a66597.h b/include/linux/usb/r8a66597.h
index 26d2167..6e1bfae 100644
--- a/include/linux/usb/r8a66597.h
+++ b/include/linux/usb/r8a66597.h
@@ -31,6 +31,9 @@ struct r8a66597_platdata {
/* This callback can control port power instead of DVSTCTR register. */
void (*port_power)(int port, int power);
+ /* This parameter is for BUSWAIT */
+ u16 buswait;
+
/* set one = on chip controller, set zero = external controller */
unsigned on_chip:1;
--
1.7.6
--
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