Re: Questions about USB core reset behavior

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On Mon, Apr 25, 2011 at 03:36:05PM -0400, Alan Stern wrote:
> On Mon, 25 Apr 2011, Alan Stern wrote:
> 
> > >  I
> > > assume that means we won't clear the TT buffer for the EHCI roothub,
> > > since this platform has a rate matching hub?
> > 
> > On the platform you're talking about, the root hub does not have a TT.  
> > On the other hand, we _will_ clear the TT buffers in the rate-matching
> > hub when they need it.
> 
> BTW, why does Intel call it a "rate-matching" hub?  In what sense does 
> it match rates?
> 
> Do they mean that it can match the high-speed upstream connection to
> the host controller with the downstream connection to a full- or
> low-speed device?  And if they do, why mention it specially?  The
> USB-2.0 specification requires all high-speed hubs to be capable of
> doing this.

AFAICT, if Intel advertises a rate matching hub on an EHCI host, they
just mean it doesn't have an OHCI/UHCI companion controller.  Perhaps
they mean the high speed PHY "matches" the rate of the low/full speed
devices?  It's all marketing speak, I think.

Sarah Sharp
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