On Wed, Nov 10, 2010 at 7:37 PM, Felipe Balbi <balbi@xxxxxx> wrote:
> Hi,
>
> On Tue, Nov 09, 2010 at 10:53:41PM -0600, Cai, Cliff wrote:
>>>
>>> It seems in double buffer mode the Blackfin MUSB controller
>>> needs about 50us delay between the packet RX interrupt and RX
>>> buffer reading operation. Otherwise, wrong data is read out of
>>> the MUSB RX buffer. Single buffer mode has no such problem.
>>> So, we are looking for a way to set up single buffer mode
>>> under MUSB framework if the original patch against 1.9 and
>>> less MUSB version doesn't work for others.
>>
>> Yes,to disable double buffering is the original purpose of my patch.
>> And since there is no control bits to implement it,we have to do this.
>
> would you please dump the fifo configuration table from hw.
>
Sorry, I am not sure of your mean.
Our endpoints fifo info can be found at musb_core.h
512 static inline int musb_read_fifosize(struct musb *musb,
513 struct musb_hw_ep *hw_ep, u8 epnum)
514 {
515 musb->nr_endpoints++;
516 musb->epmask |= (1 << epnum);
517
518 if (epnum < 5) {
519 hw_ep->max_packet_sz_tx = 128;
520 hw_ep->max_packet_sz_rx = 128;
521 } else {
522 hw_ep->max_packet_sz_tx = 1024;
523 hw_ep->max_packet_sz_rx = 1024;
524 }
525 hw_ep->is_shared_fifo = false;
526
527 return 0;
528 }
--
Thanks,
--Bob
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