On Tue, 2010-03-02 at 17:05 +0000, Catalin Marinas wrote: > The viable solutions so far: > > 1. Implement a PIO mapping API similar to the DMA API which takes > care of the D-cache flushing. This means that PIO drivers would > need to be modified to use an API like pio_kmap()/pio_kunmap() > before writing to a page cache page. > 2. Invert the meaning of PG_arch_1 to denote a clean page. This > means that by default newly allocated page cache pages are > considered dirty and even if there isn't a call to > flush_dcache_page(), update_mmu_cache() would flush the D-cache. > This is the PowerPC approach. I don't see the point of a "PIO" API. I would thus vote for 2 :-) Note that flushing the D-cache isn't enough, you also need to invalidate the I-cache as we discussed earlier, though you mostly get away if you don't by luck. There's also a question as to whether clearing PG_arch_1 is flush_dcache_page() is really necessary or not. > Option 2 above looks pretty appealing to me since it can be done in the > ARM code exclusively. I've done some tests and it indeed solves the > cache coherency with a rootfs on a USB stick. As Russell suggested, it > can be optimised to mark a page as clean when the DMA API is involved to > avoid duplicate flushing. That wouldn't solve the need for invalidating the I-cache... Unless we use another bit. > It was also suggested to add a PG_arch_2 flag which would keep track of > the I-cache status as well. > > I can post a proposal to modify the cachetlb.txt document to reflect the > issues we currently have on ARM. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
