On Wed, 03 Mar 2010 10:29:54 +1100 Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx> wrote: > On Tue, 2010-03-02 at 17:05 +0000, Catalin Marinas wrote: > > > The viable solutions so far: > > > > 1. Implement a PIO mapping API similar to the DMA API which takes > > care of the D-cache flushing. This means that PIO drivers would > > need to be modified to use an API like pio_kmap()/pio_kunmap() > > before writing to a page cache page. > > 2. Invert the meaning of PG_arch_1 to denote a clean page. This > > means that by default newly allocated page cache pages are > > considered dirty and even if there isn't a call to > > flush_dcache_page(), update_mmu_cache() would flush the D-cache. > > This is the PowerPC approach. > > I don't see the point of a "PIO" API. I would thus vote for 2 :-) Note Yeah, as powerpc and ia64 do, arm can flush D cache and invalidate I cache when inserting a executable page to pte, IIUC. No need for the new API for I/D consistency. The ways to improve the approach (introducing PG_arch_2 or marking a page clean on dma_unmap_* with DMA_FROM_DEVICE like ia64 does) is up to architectures. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
