On 8/25/24 07:22, Thomas Gleixner wrote:
On Thu, Aug 22 2024 at 23:25, Mario Limonciello wrote:
Why is this hidden in a reply to the middle of a PCI patch series?
Sigh.
As I mentioned in my reply I didn't mean for this to go out at this
time. Sorry for the noise!
It's still under testing that it REALLY helps things.
It was in my working directory and I totally missed it when I sent this
PCI series.
From: Mario Limonciello <mario.limonciello@xxxxxxx>
On AMD processors the TSC has been reported drifting on and off for
various platforms. This has been root caused to becaused by out of order
TSC and HPET counter values. When the SoC supports RDTSCP or LFENCE_RDTSC
use ordered tsc reads instead.
This really wants a fixes tag.
Yes; assuming it really helps I will send it properly with tags and to
the right lists.
