On Thu, Aug 22 2024 at 23:25, Mario Limonciello wrote: Why is this hidden in a reply to the middle of a PCI patch series? Sigh. > From: Mario Limonciello <mario.limonciello@xxxxxxx> > > On AMD processors the TSC has been reported drifting on and off for > various platforms. This has been root caused to becaused by out of order > TSC and HPET counter values. When the SoC supports RDTSCP or LFENCE_RDTSC > use ordered tsc reads instead. This really wants a fixes tag.
