From: Mario Limonciello <mario.limonciello@xxxxxxx> On AMD processors the TSC has been reported drifting on and off for various platforms. This has been root caused to becaused by out of order TSC and HPET counter values. When the SoC supports RDTSCP or LFENCE_RDTSC use ordered tsc reads instead. Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx> --- arch/x86/include/asm/tsc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 94408a784c8e7..1c0cda1702bec 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -24,6 +24,9 @@ static inline cycles_t get_cycles(void) if (!IS_ENABLED(CONFIG_X86_TSC) && !cpu_feature_enabled(X86_FEATURE_TSC)) return 0; + if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC) || + cpu_feature_enabled(X86_FEATURE_RDTSCP)) + return rdtsc_ordered(); return rdtsc(); } #define get_cycles get_cycles -- 2.43.0
