Hello Thinh, On Fri, 17 Nov 2023 01:55:30 +0000 Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> wrote: > Hi, > > Sorry, email client issue with your email. Attempt to resend: Thanks for your quick reply. > > On Fri, Nov 17, 2023, Thinh Nguyen wrote: > > Hi, > > > > On Thu, Nov 16, 2023, Köry Maincent wrote: > > > On Thu, 16 Nov 2023 17:42:06 +0100 > > > Köry Maincent <kory.maincent@xxxxxxxxxxx> wrote: > > > > > > > Hello, > > > > > > > > Similar issue with ZynqMP board related to that patch: > > > > > > > > xilinx-psgtr fd400000.phy: lane 3 (type 1, protocol 3): PLL lock timeout > > > > phy phy-fd400000.phy.3: phy poweron failed --> -110 > > > > dwc3 fe300000.usb: error -ETIMEDOUT: failed to initialize core > > > > > > > > With CONFIG_USB_DWC3_DUAL_ROLE and dr_mode = "host"; > > > > > > > > It may not be the correct fix. > > > > > > Just figured out there was a patch (357191036889 usb: dwc3: Soft reset > > > phy on probe for host) from Thinh aimed to fix it but the issue is still > > > here on ZynqMP. > > > > > > > How many ports do you use? Can you try this: I am using 2 ports. I will test it out next week as I don't have access to the board until then. Regards, -- Köry Maincent, Bootlin Embedded Linux and kernel engineering https://bootlin.com
