R: basic doubt on root hubs (on an embedded SoC)

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Hi,

in my understanding, the statement:

"The full-speed and low-speed operations are supported through the EHCI software stack via a transaction translation layer."

mean that as many other usb controller, no hardware ttl is provided. So i see two possibilities:

- Use the ttl in software (as datasheet say), perhaps already provided with some kind of libraries by your vendor or
- Use an usb hub, so with an hw ttl.

Have a good day

--- Mer 25/11/09, Mandeep Sandhu <mandeepsandhu.chd@xxxxxxxxx> ha scritto:

> Da: Mandeep Sandhu <mandeepsandhu.chd@xxxxxxxxx>
> Oggetto: basic doubt on root hubs (on an embedded SoC)
> A: "linux-usb" <linux-usb@xxxxxxxxxxxxxxx>
> Data: Mercoledì 25 novembre 2009, 08:30
> Hi All,
> 
> I have a basic doubt on root hubs.
> 
> I'm working on a media SoC which has 1 USB interface which
> can
> function both as a host and a device (would this qualify
> for OTG? the
> datasheet doesn't mention OTG though) and an on-chip PHY.
> Here's an
> excerpt from the datasheet about the USB host controller:
> 
> "The USB 2.0 Embedded Host Controller is fully compliant
> with the USB
> 2.0 specification and the Enhanced Host Controller
> Interface (EHCI)
> specification revision 1.0. The controller supports
> high-speed
> (480Mbps) transfers. The controller comprehends the
> high-speed,
> full-speed and low-speed data ranges providing
> compatibility with a
> full range of USB devices. The full-speed and low-speed
> operations are
> supported through the EHCI software stack via a
> transaction
> translation layer."
> 
> Now my question is, does the EHCI also function as a root
> hub? As in
> the root hub is incorporated into the host controller?
> 
> If I have to add another USB port to such a device, will it
> be
> possible to connect it to the existing root hub?
> 
> I'm asking this because its mentioned that the host
> controller also
> has an on-chip PHY, and as I understand I'll have to
> connect my second
> port directly onto the USB bus and not to the PHY
> interface. Is my
> understanding correct?
> 
> Thanks,
> -mandeep
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